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NXP Semiconductors /LPC43xx /CGU /PLL1_STAT

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Interpret as PLL1_STAT

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https://regviz.com/r/NXP Semiconductors/LPC18xx/CGU/PLL1_STAT#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LOCK)LOCK 0RESERVED

Description

PLL1 status register

Fields

LOCK

PLL1 lock indicator
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data